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RFIC Layout Engineer
Category: Computing, Publishing
  • Your pay will be discussed at your interview

Job code: lhw-e0-85008354

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  Job posted:   Sat Feb 24, 2018
  Distance to work:   ? miles
  3 Views, 0 Applications  
RFIC Layout Engineer

# RFIC Layout Engineer

Job Number: 113514691

Santa Clara Valley, California, United States

Posted: 22-Feb-2018

Weekly Hours: 40.00

**Job Summary**

In this role, you will work closely with the RFIC design team to layout and verify custom RF and analog IP

for complex SoC products.

**Key Qualifications**

* Positions are available for multiple experience levels.

* Preferred experience in custom RF/analog layout with extensive knowledge on deep subK micron CMOS (40nm, 28nm, etc.).

* Capability to lead other layout engineers for top level integration.

* Knowledgeable on layout techniques for device matching, minimizing parasitics, RF shielding, and high frequency routing.

* Must understand issues of RC delay, electro-migration, and cross capacitance.

* Must understand guard rings, DNW, PN junctions, and advanced process effects such as LOD, WPE, etc.

* Must recognize failure prone circuit and layout structures, proactively work with circuit designer for best approach to problems.

* High level proficiency in interpretation of CALIBRE DRC, ERC, LVS, etc.

* Knowledge of CADENCE layout tools.

* Scripting skills in PERL or SKILL or AMPLE are considered a plus, but not required.

* Excellent communication skills and able to work with cross-functional teams.


o Detailed transistor level layout of RF and analog circuit blocks including LNA, mixers, PLL, LO

generation, modulators, power amplifiers, ADC/DAC, baseband filters, and bandgap/bias/LDO.

o Layout of sensitive analog components including resistors, capacitors, and inductors.

o Block level and top level layout through full verification flow including RCLK extraction, DRC, LVS, and

DFM checking.

o Collaborate with designers on block level and top level floor planning.

o Layout review for power/gnd routing, electro-migration, signal path check, differential and IQ matching,

and signal coupling.

o Top level layout integration and verification, schedule management.


BSEE or equivalent

**Additional Requirements**

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